1. Field of the Invention
This invention relates to information storage systems and particularly to integrated capacitive storage systems.
2. Description of the Prior Art
Designers of memory systems used in data processing systems have long been aware of the potential of utilizing small capacitors to store binary information. Most of the previously described capacitive storage systems have failed to meet with expected commercial success in view of certain processing or circuit complexity limitations inherently found in the systems.
U.S. Pat. No. 2,828,447, entitled, "Neon Capacitor Memory System," issued Mar. 25, 1958, to J. W. Mauchly, teaches the use of a memory storage matrix which includes memory cells comprising a capacitor and a bilateral conducting neon gas tube. Information is stored on a plurality of capacitors directly coupled to a common bit/sense line. Each gas tube acts as a threshold dependent switching element.
U.S. Pat. No. 3,196,405, entitled, "Variable Capacitance Information Storage System," issued July 20, 1965, to J. B. Gunn and assigned to the assignee of the instant invention, teaches a capacitive memory system utilizing a pair of diodes, connected front-to-back, and a capacitor to form a memory cell. Although the memory provides nondestructive readout, bipolar control signals are necessary and data inversion takes place upon readout.
U.S. Pat. No. 3,553,658, entitled, "Active Storage Array Having Diodes for Storage Elements," issued Jan. 5, 1971, to W. D. Pricer and assigned to the instant assignee, teaches the use of a capacitive memory cell comprising only two back-to-back connected diodes.
The article, "Vertical Diode-Capacitor Memory Cells," W. H. Chang et al., IBM Technical Disclosure Bulletin, February 1973, pages 289-9, teaches an integrated capacitive memory cell which includes a single diode and capacitor.
Both of the last two referred to memory systems utilizing diodes have the disadvantage of requiring avalanche or reverse breakdown of the rectifying diode junction which leads to long term instability and reliability problems unless the signal voltage/drive voltage ratio of the system is reduced below optimum levels.
U.S. Pat. No. 3,387,286, entitled, "Field Effect Transistor Memory," issued June 4, 1968, to R. H. Dennard and assigned to the present assignee, describes an array of semiconductor memory cells each comprising only a single field effect transistor (FET) coupled to a storage capacitor. The FET acts as a gating element and has its drain electrode connected to a bit/sense line and its gate electrode connected to a word line. The storage capacitor is coupled between the source electrode of the FET and a reference potential. Integrated semiconductor memory chips utilizing single FET/capacitor memory cells are presently feasible which contain in excess of 16,000 binary bits and conceivably can be fabricated to the maximum limits of photo-processing technology. An inherent problem in the use of FET elements in memory cells is their comparatively slower operation than more conventional less dense multi-element bipolar memory cells.
U.S. Pat. No. 3,876,992, entitled, "Bipolar Transistor Memory with Capacitive Storage," issued Apr. 8, 1975, to W. D. Pricer, and assigned to the instant assignee, discloses an integrated memory cell comprising only a single bipolar transistor and a capacitor. Although each memory cell includes a bipolar device and its necessary isolation regions, significant improvements in density over previously known bipolar cells are achievable while retaining the inherent speed of bipolar semiconductor technology.
Another variation in the integrated capacitive storage area is taught in U.S. Pat. No. 3,676,715, entitled, "Semiconductor Apparatus for Image Sensing and Dynamic Storage," issued July 11, 1972, to S. Brojdo, which describes the use of a PN-junction diode coupled with a depletion voltage variable capacitor as a storage element. Stored information is represented by the presence or absense of carriers in a depletion region created by a field effect gate electrode. In order to write logical "1's" and "0's" into the storage cell a two step operation is necessary which undesirably causes the cycle time to be extended.
Another version of the FET/capacitor memory cell is disclosed in U.S. Pat. No. 3,705,391, entitled, "Memory System Employing Capacitance Storage Means," issued Dec. 5, 1972, to R. H. Baker, which describes the use of a plurality of independently accessible FET devices serially connected through storage capacitances to a common input/output line. The memory system is organized and operates in a similar manner to that of the Dennard reference referred to above except that one of the conducting electrodes of the FET device is connected to a source of reference potential.
In summary, although numerous variations of capacitive memory storage elements have been previously disclosed, there exists certain inherent limitations in these systems which prevents their efficient application in data processing information storage systems. And while each of the above techniques utilizes only a single active switching device and a single capacitor as a memory cell to achieve maximum density, the bipolar device versions are limited somewhat in density due to the requirement of isolation regions while the FET versions are limited in their performance. The diode/capacitor memory cells utilizing avalanche breakdown present a reliability problem.